With SC300 security core processor and the basic frequency up to 204MHz, MH1903S makes full use of its excellent architectural characteristics and the high performance so as to achieve the high performance and provide the safe and energy-saving solutions.
With the built-in security encryption module, the chip supports a variety of encryption security algorithms, including DES, TDES, AES, RSA, ECC, SHA, and other encryption algorithms. The chip hardware also supports a variety of attack detection functions, and conforms to the financial security equipment standards.
The chip contains the BOOT program, supporting the verification of firmware signature upon downloading and starting. In addition to the built-in 640KB SRAM, the chip also integrates abundant peripheral resources, including Smartcard, magnetic stripe card decoding, security keyboard, LCDI, DCMI, etc. All the peripheral driver software is compatible with the current mainstream security chip software interface and in line with ARM CMSIS specification. The users can develop and transplant quickly on the basis of the existing solutions.
Secure SoC Megahunt MH1903S
ARM SecurCore™ SC300™ core:
- 32-bit RISC Core (ARMv7-M)
- MPU memory protection unit
- Maximum basic frequency of 204MHz (adjustable for 1 and 2 frequency division)
- FPU unit
- 1 controlled JTAG-DP/SW-DP debugging port
- 640KB SRAM
1 QSPI controller, supporting XIP
System control module (To control all peripheral module clocks and system-related configurations)
Security encryption algorithm accelerator engine
Symmetric algorithms: DES, TDES, AES-128/192/256
Asymmetric algorithm: RSA-1024/2048, ECC
HASH check algorithm: SHA-1/224/256/384/512 - Interfaces:
- - 2x SmartCard interfaces (supporting EMV level-1 protocol specification, ISO7816-3 standard), where SCI0 integrates 7816 level conversion function, and can be configured with output of 3V and 1.8V
- 4x UART interfaces (Supporting 4 lines)
- 3x SPI interfaces (Where SPI0 can be configured as master and slave, the other 2 interfaces only support Master)
- 1x high-speed SPI Master interface SPI5 - - 1x IIC interface
- 1x KBD (4x5 matrix keyboard)
- 8x 32-bit TIMER (With PWM function, supporting single-cycle output)
- 1x LCDI interface, supporting 8080 and 6800 bus protocol
- 1x true random number generator
- 1x DMA controller (supporting 8-channel DMA transmission)
- 1x CRC module (Supporting 16Bit/32Bit, a variety of common polynomial calculation)
- Support up to 87 GPIOs
- Support up to 8 static Tampers or 4 groups of dynamic Tampers (4 outputs, 4 inputs), dynamic/static state configurable
- 1x group of internal Sensors (Supporting high and low voltage, high and low temperature, Mesh, clock and voltage glitch detection)
- 1x secret key storage area (Supporting rapid erase of hardware)
- 1x USB (OTG-FS)
- Support USB2.0 and OTG1.0a
- Built-in USB PHY module
- Private interrupt vector, to accelerate the data communication speed
- Integrated internal watchdog
- 1x 10-bit DAC interface
- 1x 7-channel 12-bit ADC, supporting up to 857 KHz sampling rate (channel 0 used for acquisition of CHARGE_VBAT voltage, the other channels used for acquisition for voltage ranging from 0 ~ 1.8V of 0 ~ 3.6V, which are configurable).
- Support magnetic stripe decoding function, support the standard cards such as ISO/ABA, AAMVA, IBM and JIS II
- 1x DCMI interface - Power:
- The chip integrates a LDO with up to 150mA output current
- The chip integrates USB charging management module, supporting the maximum charging current of 200 mA
- The chip integrated the power-on/off function
- Support the output of 27.12M frequency
