With 32 bit security core processor and the basic frequency up to 144MHz, MH1902T(Ares) makes full use of its excellent architectural characteristics and the high performance so as to achieve the high performance and provide the safe and energy-saving solutions.
With the built-in security encryption module, the chip supports a variety of encryption security algorithms, including DES, TDES, AES, RSA, ECC, SHA, and other encryption algorithms. MH1902T(Ares) also supports a variety of attack detections, and conforms to the financial payment equipment safety standards.
Ares contains the safety BOOT program, supporting the verification of firmware signature upon downloading and starting. In addition to the built-in 128KB SRAM, Ares also integrates abundant peripheral resources, including Smartcard, magnetic stripe card decoding, security keyboard, etc. All the peripheral driver software is compatible with the current mainstream security devices interfaces . The users can develop and transplant quickly on the basis of the existing solutions.
With advanced manufacturing process, Ares can provide higher working frequency and lower power consumption, which are ideal for the design of sorts of smart terminals.
32-bit RISC Core
- 32-bit RISC Core
- MPU memory protection unit
- 144/120/108/72/60/54MHz frequencies（adjustable for 1/2/4 frequency division）
- 1x controlled JTAG-DP/SW-DP debugging port
128KB build-in SRAM
System control module (To control all peripheral module clocks and system-related configurations)
Security encryption algorithm accelerator engine
- Symmetric algorithms：DES、TDES、AES-128/192/256
- Asymmetric algorithms：RSA-1024/2048、ECC
- HASH check algorithm：SHA-1/224/256/384/512
3x UART interfaces (Supporting 4 lines)
1x SmartCard interface (supporting EMV level-1 specification, ISO7816-3 standard), where
SCI0 integrates 7816 level conversion function, and can be configured with output of 3V and 1.8V
3x SPI interfaces (one can be configured as master or slave, another 2 interfaces support only Master)
One high-speed SPI interface SPI3(mater/slave configurable)
One I2C interface
Six 32-bit TIMER (With PWM function)
One true random number generator
One DMA controller (supporting 4-channel DMA transmission)
One CRC module (Supporting 16Bit/32Bit, a variety of common polynomial calculation)
Support up to 8 static Tampers or 4 groups of dynamic Tampers (2 outputs, 2 inputs), dynamic/static state configurable
One group of internal Sensors (Supporting detection of high and low voltage, high and low temperature, Mesh, clock and voltage glitch)
Secret key storage area (Supporting rapid erase)
One USB（OTG-FS）
- USB2.0 and OTG1.0a
- Built-in USB PHY
- Dedicated DMA channel and interrupt vector, to speed-up the data communication
Built-in watchdog
One 10-bit ADC with 7 channels. supporting up to 1MHz sampling rate. Channel 0 is used for acquisition of voltage ranging from 0~5V(internal bleeder 1.7M/425K) , while other channels are used for acquisition for voltage ranging from 0 ~ 1.2V.
One 10bit DAC
Built-in magnetic stripe card decoding module, supporting the standard cards such as ISO/ABA, AAMVA, IBM and JIS II
Built-in USB charging management module, supporting charging current up to 200 mA
Built-in the power-on/off function
Support the output of 27.12M frequency
