The MH7256 (256M-bit) is a serial interface Flash memory device designed for operating on a single power supply from 2.3-3.6V with current consumption as low as 0.2μA at deep power-down in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the device with its page erase granularity is ideal for data storage as well, eliminating the need for additional data storage devices.
There are 131,072 programmable pages (256-Bytes each) configured in the device and up to 256 Bytes can be programmed at a time. The groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase) allow Pages to be erased. The device has 8,192 erasable sectors and 512 erasable blocks respectively. The small 4KB sectors afford greater flexibility for applications requiring data and parameter to be stored.
The device support standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI), including Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP) and I/O3 (/HOLD). It also supports SPI clock frequencies up to 166MHz, allowing equivalent clock rates of 332MHz for Dual I/O and 664MHz for Quad I/O when running Fast Read Dual/Quad I/O and QPI instructions. Device also adds support for DTR (Double Transfer Rate) instructions, which can exceed the transfer rates of standard Asynchronous 8 and 16-bit Parallel Flash memories. With a 24-bit address being read in just 8-clocks of instruction overhead, the Continuous Read Mode enables efficient memory access, allowing true XIP (execute in place) operation.
Moreover, there are a Hold pin, Write Protect pin and programmable write protection with top or bottom array control to provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 128-bit Unique Serial Number and three 2048-Bytes Security Registers.
| Read performance Comparison Table | ||||||
|---|---|---|---|---|---|---|
| (STR Mode)[1] | ||||||
| Numbers of Dummy Cycles | Fast Read (0BH) (MHZ) | Fast Read Dual Output (3BH) (MHZ) | Fast Read Quad Output (6BH) (MHZ) | Fast Read Dual I/O (BBH) (MHZ) | Word Read Quad I/O (E7H) (MHZ) | Fast Read Quad I/O (EBH) (MHZ) |
| 4 | - | - | - | 108* | 108* | 108 |
| 6 | - | - | - | - | - | 166* |
| 8 | 166* | 166* | 166* | 166 | 166 | 166 |
| 10 | - | - | - | - | - | 166 |
| (DTR Mode)[1] | ||||||
| Numbers of Dummy Cycles | DTR Fast Read (0DH) (MHZ) | DTR Fast Read Dual I/O (BDH) (MHZ) | DTR Fast Read Quad I/O (EDH) (MHZ) | |||
| 4 | 66 | 66 | 66 | |||
| 6 | 90* | 90* | 66 | |||
| 8 | 90 | 90 | 90* | |||
| 10 | 108 | 108 | 108 | |||
Note:
[1] * Mean default status;
