Firefly Core-3588L (JL, ML)

Up to 6 TOPs (INT8), Support INT4/INT8/INT16 mixed operations, Support framework switching of TensorFlow / MXNet / PyTorch / Caffe

48MP ISP with HDR & 3DNR

Hardware decoding: 8K@60fps H.265/VP9/AVS2, 8K@30fps H.264 AVC/MVC, 4K@60fps AV1, 1080P@60fps MPEG-2/-1/VC-1/VP8

Hardware encoding: 8K@30fps H.265 / H.264

eMMC (32GB/64GB/128GB/256GB optional)

4V (voltage tolerance ± 5%)

Android and Linux OS

LGA package, a total of 506 pins, a 12-layer PCB design

45 mm * 50 mm

≈20 g

GMAC/SDIO 3.0/USB 3.0 can expand Gigabit Ethernet, WiFi 6/Bluetooth, and 5G/4G LTE

4 * MIPI CSI DPHY (DPHY V1.2 (2 lanes, 2.5Gbps /lane ); 2 sets of 2-lane DPHY can be combined into 1 set of 4-lane DPHY)

2 * MIPI D/CPHY (MIPI DPHY V1.2 (4 lanes, 2.5Gbps/lane); MIPI CPHY V1.1 ( 3 lanes, 2.5 Gsps/lane))

1 * HDMI RX (supporting HDMI 2.0 (3.4 Gbps~6 Gbps ); HDMI 1.4b (250 Mbps~3.4 Gbps); HDCP 2.3 and HDCP1.4)

1 * DVP (8/10/12/16-bit standard DVP, with a maximum 150MHz data input; supporting BT.601/BT.656 and BT.1120 VI interface)

2 * HDMI2.1 TX/eDP1.3 TX (one 8K@60Hz HDMI supporting HDCP2.3; eDP1.3, 4K@60Hz, supporting HDCP1.3; HDMI and eDP unable to work simultaneously)

2 * DP1.4a (shared with USB3.1 Gen1, supporting 1, 2, 4 lanes; up to 7680 * 4320@30Hz; HDCP2.3, HDCP 1.3)

2 * MIPI DSI (supporting MIPI DPHY 2.0 or CPHY 1.1, 4K@60Hz; dual MIPI displays (left-right), and RGB/YUV formats (up to 10 bits))

1 * BT.1120 output (supporting RGB format (up to 8 bit), with a data rate of up to 150MHz and resolution up to 1920 * 1080@60Hz)

Support 7 displays (achieve up to 7 displays (2 * HDMI + 2 * MIPI DSI + 2 * DP (one DP can be converted to VGA) + 1 * BT.1120))

2 * I2S (8 lanes), supporting TX and RX, audio resolution ranging from 16 to 32 bit, and a sampling rate of up to 192 KHz)

2 * I2S( 2 lanes), supporting TX and RX, audio resolution ranging from 16 to 32 bit, and a sampling rate of 192 KHz)

2 * SPDIF, supporting 2×16 bit audio data storage and dual-phase stereo output

2 * PDM (8 lanes), up to 8 channels, audio resolution of 16 to 24 bit, a sampling rate of up to 192 KHz; PDM master receive mode, and multiple MIC arrays

3 * SATA 3.0 shared with PCIe 2.1

3 * PCIe2.1(1 lane), shared with SATA 3, only supporting RC (Root Comple), with a maximum data rate of 5 Gbps

1 * PCIe3.0 (2×2, 1×4, 4×1) 4 options: 1*4 lanes / 2*2 lanes / 4*1 lane / (1*2 lanes + 2*1 lane); each lane supports 8 Gbps data rate;

supporting RC and EP

2 * USB 3.1 OTG (shared with DP (USB3OTG_0 and USB3OTG_1) ), 1 * USB 3.1 HOST (shared with PIPE-PHY2 (USB3OTG_2) )

2 * USB2.0 HOST, 2 * USB2.0 OTG

1 * SDIO 3.0, supporting SDIO 3.0 (4-bit data bus widths)

9 * I2C, supporting 7-bit and 10-bit addressing modes, achieving data transfer rates of up to 100k bits/s in standard mode

and up to 400k bits/s in fast mode

5 * SPI: each controller supports 2 chip select outputs; offering both serial master and serial slave modes, with software configuration

10 * UART, built-in 2-channel 64 bit FIFO, used respectively for TX and RX; supporting 5-bit, 6-bit, 7-bit, and 8-bit serial data transmission, with a baud rate of up to 4 Mbps; all 10 UART channels support automatic flow control mode

3 * CAN 2.0B, supporting CAN standard frames and extended frames for transmission and reception

16 * PWM, supporting up to 16 on-chip PWM channels, with capture mode

8 * ADC, 12-bit single-ended input SAR-ADC, with a sampling rate of up to 1MS/s

All GPIOs can be used to generate interrupts.