SoC | Multi-CPU Heterogeneous Multi-app Micro-Processor Ingenic X2000 - SATRON electronics

Multi-CPU Heterogeneous Multi-app Micro-Processor Ingenic X2000

Multi-CPU Heterogeneous Multi-app Micro-Processor Ingenic X2000

X2000 is a multi-CPU heterogeneous multi-app micro-processor, designed and delivered by I ngenic Inc., Ltd. It includes both an XBurst®2 (a MI PS based I ngenic CPU core,which can be configured to work as two logic CPUs) and an XBurst®O (another I ngenic CPU core, MI PS based) combining the computing capacity of application processors with the real-time control ability and outstanding power efficiency of MC Us arid crossing over application domains.

Key Features

  • Three CPUs inside: XBurst®2 working as two logic cpus and one XBurst®O. The XBurst®2 core specializes in computing while the XBurst®O is more suitable for real time control. XBurst® is the family name of lngenic's 32bit RISC CPU cores which are based on the MIPS ISA and contain a 128bit SIMD, a FPU, a MMU and other featured modules. XBurst®2 is the latest generation.
  • Security sub-system: There is a True Random Number Generator integrated inside the chip. AES-256, RAS-2048, M 05, SHA and SHA2 are supported.
  • Memory in Chip: 128Mbytes of DRAM are in the package.
  • Advanced Connectivity: Compliant with IEEE 1588-2002, Gigabit Ether­net Media Access Controllers are included.
  • Multimedia Processing Ability: The VPU has the capacity of video coding and decoding in compliance with H.264, the resolution being up to 1080p@30fps. 2 ISPs are embedded while synchronization between two camera serisors is supported.
  • Peripheral Interfaces: There are interfaces built in the chip for audio, video, display, memory and data tranismission among other purposes.

CPU Core:

  • XBurst®2 which can be configured to work as two cores, MI PS ISA based, frequency at 1.2GHz
  • 32KB L1x2Cache, 512KBL2Cache, 32KB SRAM
  • FPU, 128bit MXA

Video Processing Unit:

  • H.264 encoder/decoder, with resolutions up to 1920x1080p@30fps
  • JPEG encoder/decoder, with processing capacity of 70Mega-pixels/s

Image Processing Units and Camera Interfaces:

  • ISP x2, support dual-camera sync.
  • CIM x1, support snapshot
  • Processing capacity of single ISP: 1080P@120fps(via MI PI-CSI 4-lane)
  • ISP Processing capacitywhileworkingtogether: 1080P@60fps / ISP
  • 3 cameras can be connected simultaneously: Ml PI-CSI 2- lane x2 + DVPx1
  • Maximum resolution for the interface: MIPI-CSI 4- lane, 1080P@120fps

Memory:

  • DRAM, 128Mbytes in package
  • SPI Flash Controller, supporting Quad & Octal SPI

Audio:

  • Digital Microphone Array Controller, supporting 8 mic channels, with voice triggering
  • I2S x3
  • PGM interface, S/PDIF

 

Display Interfaces:

  • MIPI-OSI, with the resolution up to 1920x1080@40Hz
  • SLCD, with the resolution up to 640x480@60Hz, 24BPP
  • RGB, with the resolution up to 1280x720@60Hz, 24BPP

Other Functions:

  • PWM, 16 channels
  • Interrupt controller, supporting 64 sources
  • Watchdog, with multiple choices of clock source
  • A/D converter, with a resolution of 10bit, 6 channels
  • Real time clock

Peripheral Interfaces:

  • GPIO
  • I2C x6
  • Synchronous serial interfaces (SSl)x2
  • UARTx10
  • MMC/SD/SDIO x2
  • USB 2.0 OTG
  • Gigabit Media Access Controller, in compliance with IEEE 1588- 2002

Security and Real Time Control System:

  • An Exclusive Core XBurst®O, 240MHz
  • True Random Number Generator
  • Supporting AES-256/RSA-2048/M D5/SHA/SHA

Package:

  • BGA270
  • 12mm x 12mm x 1.2mm, 0.65mm Pitch